This application claims priority to Korean Patent Application No. 2003-26427, filed on Apr. 25, 2003.
1. Field of the Invention
The present invention relates to a content addressable memory cell; particularly, a content addressable memory device having redundant array for replacing a defective cell and a ternary content addressable memory capable of storing three states of information.
2. Discussion of Related Art
Semiconductor memories include RAMs, ROMs, and content addressable memories (hereafter referred to as “CAMs”). While RAMs and ROMs use addresses to indicate specific cells within the memory cell array to access data therein, CAMs receive data instead of addresses. The data input to the CAM is compared with data stored in all the cells simultaneously, and the matched result is the address. The CAM is commonly used in applications requiring fast searches for a pattern, a list, image data, etc.
Binary CAM cell and ternary CAM (TCAM) cell are different types of CAMs. A typical binary CAM cell is configured like a RAM cell to store one of two states of information, i.e., a logic “1” state and a logic “0” state. The binary CAM cell includes a compare circuit that compares externally supplied data (hereinafter, ‘search data’) with data stored in the RAM cell and drives a corresponding match line to a predetermined state when the search data and the stored data are matched. Examples of the binary CAM cells are disclosed in U.S. Pat. No. 4,646,271, U.S. Pat. No. 4,780,845, U.S. Pat. No. 5,490,102, and U.S. Pat. No. 5,495,382. A TCAM cell can store one of three states of information, i.e., a logic “1” state, a logic “0” state, and a “don't care” state. An example of the ternary CAM cell is disclosed in U.S. Pat. No. 5,319,590.
FIG. 1 shows a conventional TCAM cell. To perform a write operation, data to be stored in the CAM cell is loaded onto bit line pairs BL1, /BL1, and BL2, /BL2. The word line WL is asserted active logic ‘1’ turning on n-channel access transistors Q1, Q2, Q3 and Q4. The data carried on the complementary bit line pairs is thereby written into the two SRAM cells and the word line is de-asserted.
For a read operation, the word line is asserted an active logic ‘1’ and the data from the SRAM cells is read onto the bit line pairs. The data then is transferred to data buses (not shown).
For a search and compare operation, the match line is pre-charged to a logic ‘1’ and the search data is placed on the search line pair SL1 and /SL1. Typically, search data and stored data are provided in such a manner that if there is a mismatch a change occurs in the match line state. The match line ML is pre-charged to a logic ‘1’ and a mismatch discharges the match line to ground, whereas in the case of a match no change occurs in the state of the match line.
If the CAM cell MC11-1 stores a logic ‘1’ in the left SRAM cell and a logic ‘0’ in the right SRAM cell, and SL1 has a logic ‘1’, and /SL1 has a logic ‘0’, a mismatch will result. The output of the left SRAM cell provides a logic ‘1’ to a transistor Q6 and turning it on. The search line SL1 provides a logic ‘1’ to a transistor Q5 and turning it on. Since Q5 and Q6 are both turned on, they provide a path to discharge the match line ML to ground and thus indicate a mismatch.
If the CAM cell stores a logic ‘0’ in the left SRAM cell and a logic ‘1’ in the right SRAM cell, a match condition will result. The output of the left SRAM cell provides a logic ‘0’ to the gate of transistor Q6 and leaving it turned off. The search line SL1 provides a logic ‘1’ to the gate of transistor Q5 and turning it on. Since Q5 and Q6 are serially connected, a path to ground does not exist for discharging the match line ML to ground. Similarly, the right SRAM cell provides a logic ‘1’ to the transistor Q8 and turning it on. The search line /SL1 provides a logic ‘0’ to the transistor Q7 and leaving it turned off. Therefore, similarly to the left SRAM cell, transistors Q7 and Q8 do not provide a path to discharge the match line ML to ground. As a result, the match line remains pre-charged to a logic ‘1’, indicating a match condition.
If the CAM cell stores a logic ‘0’ in both the right and left SRAM cells, a “don't care” state exists. The output from each SRAM cell produces a logic ‘0’. The logic ‘0’ is provided to the gate of transistors Q6 and Q8, ensuring that a don't care condition is detected regardless of the data provided on the search line pair SL1 and /SL1, and the match line remains unchanged.
Although TCAMs provide advantages such as speedy access for numerous applications, there are performance and reliability issues which can be inproved upon. For example, if the match line is pre-charged to a logic ‘1’ and the CAM cell stores a logic ‘0’ in the right SRAM cell and the search line /SL1 provides a logic ‘1, then the voltage level of the match line ML fluctuates. This is because the voltage level floats between the transistor Q7 and the transistor Q8.
In addition, a CAM is rendered inoperable or unusable when there are defective cells. For example, a cell may become defective during the manufacturing process or operation of the CAM. To increase manufacturing yield, other memories such as SRAM and DRAM have provided redundant memory arrays to replace the defective memory cells. When memory cells in an array are defective or become defective, a redundant memory array replaces the array with the defective cell and the data is accessed to and from the redundant memory array. Fuses are generally provided in memories having redundant arrays to switch the arrays into the memory device. When replacement is needed, the fuses for the defective rows are then blown to disable the defective rows, thereby preventing access to the defective rows. An example of a redundancy scheme in a CAM is disclosed in U.S. Pat. No. 6,445,628.
In view of the foregoing, a need exists for a CAM circuit and method capable of stable and redundant operations.